Accelerating to 112 Gbps PAM4 Webinar : A Real-World FPGA Implementation

Accelerating to 112 Gbps PAM4 Webinar : A Real-World FPGA Implementation

 

Accelerating data channels to 112 Gbps PAM4 forces system designers to balance increasing throughput, scalability and density demands with concerns such as signal integrity, system architectures and time-to-market. In this webinar, technical experts from Achronix and Samtec will discuss real-world tools and solutions that optimize the signal path both inside and outside the system design. Achronix and Samtec will provide a real-world case study of implementing 112Gbps PAM4 links using the Achronix Speedster®7t FPGA and Samtec’s portfolio of high performance interconnect solutions.

You will learn:

  • What emerging applications that require 112 Gbps signals
  • How to optimize the FPGA SerDes settings for optimal signal integrity
  • Key design considerations when designing your board interconnect

Presented by:
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Matthew Burns - Technical Marketing Manager, Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon to Silicon solutions, and over the course of the last 20 years he has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

 
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Alan Hilton-Nickel, Sr. SI Engineer, Achronix

Alan Hilton-Nickel brings 30 years of experience in Signal Integrity, System Development and Electronics Manufacturing to his role at Achronix, developing high-speed Test and Measurement boards and Reference boards. He holds a Bachelor’s degree in Electrical Engineering from the University of Calgary in Canada.