Maximize Performance Using FPGAs with PCIe Gen5 Interfaces

Maximize Performance Using FPGAs with PCIe Gen5 Interfaces

 

In this webinar, you will learn how to maximize design performance using FPGAs with embedded PCIe Gen5 interfaces. You’ll see why, in addition to high-speed connectivity, you need the ability to process incoming high-bandwidth data to accelerate application performance. You'll learn how to maximize application bandwidth using FPGAs that include:

 

  • Embedded PCIe Gen5 x16 interfaces capable of 512 GT/s
  • High-speed network on chip capable of delivering more than 20 Tbps of bandwidth
  • High-performance GDDR6 memory interfaces
  • Optimized arithmetic units designed to support number formats needed for AI / ML workloads

We will also highlight several application use cases for PCIe Gen5 enabled FPGAs along with important FPGA design considerations to ensure maximum efficiency and bandwidth.

 

Presented by:
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Kent Orthner - Senior Director Systems Engineering

Kent Orthner has worked in the IP, semiconductor, and embedded industry for over 20 years, with a focus on all aspects of interconnect, IP interoperability, and FPGA design. Prior to joining Achronix, Kent was the Vice President of Engineering at Arteris, where he developed and released the highly scalable and configurable Ncore cache-coherent SoC interconnect IP. Before that, Kent worked at Altera for 11 years, where he led the development of the Qsys System Integration platform and the SystemConsole debug infrastructure. At Achronix, Kent contributes to leading-edge FPGA architecture and SoC integration. Kent holds a B.A.Sc. from the University of Ottawa, and a M.Eng from Carleton University, in Computer and Electrical Engineering, respectively.