Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip

An FPGA Architecture Built for Bandwidth

This novel architecture has hundreds of NoC-access-points located throughout the FPGA core that can access off-chip memories and any of the high-speed PCI Express ports. This family of FPGAs also include specialized modes for the high-speed 400G Ethernet ports.

In addition, you will see how data can be streamed across the FPGA fabric using 512 Gbps NoC channels located throughout the FPGA processing array.

Presented by:

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Kent Orthner - Senior Director Systems Engineering

Kent Orthner has worked in the IP, semiconductor, and embedded industry for over 20 years, with a focus on all aspects of interconnect, IP interoperability, and FPGA design. Prior to joining Achronix, Kent was the Vice President of Engineering at Arteris, where he developed and released the highly scalable and configurable Ncore cache-coherent SoC interconnect IP. Before that, Kent worked at Altera for 11 years, where he led the development of the Qsys System Integration platform and the SystemConsole debug infrastructure. At Achronix, Kent contributes to leading-edge FPGA architecture and SoC integration. Kent holds a B.A.Sc. from the University of Ottawa, and a M.Eng from Carleton University, in Computer and Electrical Engineering, respectively.