Five Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC Webinar
The current generation of SmartNICs relies heavily upon utilizing semiconductor devices with many ARM cores (or similar) to process packets at 25GbE. This approach, which is already challenged at 25GbE, becomes even more difficult to scale to 100GbE and higher.
Enter the reconfigurable SmartNIC, a fusion of technologies bound together by a two-dimensional network on chip (2D NoC) overlayed onto a high-performance FPGA fabric. This webinar will cover five reasons why an FPGA with a 2D NoC is required for the next generation of SmartNICs including:
Scott Schweitzer, Sr. Manager, Product Planning, Achronix
Scott is a lifelong technology evangelist. He's written software products for Apple's App Store, built hardware, and managed programs for IBM, NEC, Myricom, Solarflare, Xilinx, and now Achronix. At Achronix, Scott's role is the SmartNIC Product Planning Manager. He focuses on accelerating networking and works with customers and partners to recognize new opportunities and define innovative products and solutions.